Approximate Restoring Dividers Using Inexact Cells and Estimation From Partial Remainders

Project Code :TVMAFE570

Objective

The main objective of this project is to save energy and improve overall circuit performance, approximate computation can be employed in applications that can withstand errors.

Abstract

Abstract:

To save energy and improve overall circuit performance, approximate computation can be employed in applications that can withstand errors. In comparison to other approximation designs, the two approximate divisions presented in this article have an array-based architecture, which significantly reduces hardware consumption while retaining excellent accuracy. In the first design, column-wise, proposed approximation cells are used in place of accurate restoring divider cells. The second approach computes a partial remainder using many rows of precise architecture, rounds and encrypts the partial remainder, and finally utilizes this encoded partial remainder and the divisor to describe approximate outputs. For the suggested dividers and other cutting-edge innovations, a thorough study of accuracy and performance is done. The suggested dividers introduce very little error while having a 46 and 57 percent reduction in space and power usage when compared to a precise design. To find the designs that strike the optimum balance, the trade-off between accuracy and enhanced performance is also investigated for a variety of approximation divisions. Two image processing programs are then used to illustrate the suggested dividers' accuracy.

Keywords: Approximate computing, restoring division, error analysis, image

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Specifications:

Software Requirements:

· Xilinx Vivado

Minimum Hardware Requirements:

· Microsoft® Windows 7

· Intel® i3 processor or equivalent with SSE support

· 4GB RAM

· 100 MB of available disk space

Learning Outcomes

Understanding self-timed circuit design: Gain knowledge about the concept of self-timed or asynchronous circuit design. Learn about the advantages and challenges of self-timed circuits compared to synchronous designs, including improved performance, reduced power consumption, and increased robustness against timing variations.
Familiarity with parallel adder architecture: Explore the architecture and operation of parallel adders. Understand how parallel adders perform addition operations on multiple bits simultaneously, enabling faster computation and higher throughput.
Knowledge of transmission gate logic: Learn about transmission gate logic and its suitability for implementing digital circuits. Understand the characteristics, advantages, and limitations of transmission gate logic, including low propagation delay, low power consumption, and bidirectional signal handling.
Understanding the adder components: Gain insights into the key components of a parallel adder, such as the carry propagation stage and sum calculation stage. Understand their functions, dependencies, and interconnections in achieving accurate addition results.
Analyzing self-timed circuit behavior: Explore the behavior of self-timed circuits, including the concept of handshaking protocols, delay-insensitive design, and timing independence. Understand how self-timed circuits achieve correct operation regardless of varying delays or signal arrival times.
Designing a parallel self-timed adder: Apply the knowledge gained to design a parallel self-timed adder using transmission gate logic style. Understand the design considerations, such as circuit topology, interconnectivity, and timing constraints, to ensure correct and efficient operation.
Simulation and analysis: Utilize simulation tools and techniques to validate the designed self-timed adder. Analyze its performance in terms of speed, power consumption, and robustness against timing variations. Gain hands-on experience in simulating and evaluating self-timed circuits to verify their functionality.
Evaluating trade-offs: Develop the ability to evaluate trade-offs between speed, power consumption, area utilization, and other performance metrics in self-timed adder design. Understand how design choices, such as the sizing of transmission gates and circuit topology, impact these trade-offs and make informed decisions based on the specific requirements of the adder.
Documentation and reporting: Develop effective communication skills by documenting the design process, results, and findings in a clear and concise manner. Prepare a comprehensive report summarizing the design, implementation, and performance analysis of the parallel self-timed adder using transmission gate logic style.
Critical thinking and problem-solving: Enhance critical thinking and problem-solving skills by identifying and addressing challenges and limitations in the design process. Explore alternative design techniques, optimization strategies, and circuit modifications to improve the adder's performance and address potential issues.