Approximate Radix-8 Booth Multipliers forLow-Power and High-Performance Operation
Also Available Domains Arithmetic Core|Xilinx Vivado|Xilinx ISE
Objective
The main objective of this project is to design an approximate radix – 8 booth multiplier with high speed and truncation of LSp to obtain power optimization.
Abstract
Multiplication is a technique that allows for smaller, faster multiplication circuits, by recoding the numbers that are multiplied. It is the standard technique used in chip design, and provides significant improvements over the "long multiplication" technique. In this paper, we present a high speed radix-8 booth multiplier for accelerating programs inclusive of digital filters, artificial neural networks, and different machine learning algorithms. For the computation of 3X an approximate adder has been designed to enhance the efficiency of the booth multiplication and sign extension limitation has been applied to reduce the area. The Radix-8 Booth Encoder circuit generates n/3 the partial products in parallel. By extending sign bit of the operands and generating a partial product of Radix-8 Booth Encoder multiplier is obtained.
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Paper Publishing
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