Approximate Multiplier Design using Novel Dual-Stage 4:2 Compressors

Also Available Domains Arithmetic Core|Xilinx Vivado

Project Code :TVMATO464

Objective

The main aim of this paper is to improve the speed and reduce the area for compressor architecture. This paper presents two novel approximate 4:2 compressor architectures for reducing area, delay and power dissipation in multipliers in which more than two stages of cascaded compressors are required for partial product accumulation

Abstract

Energy-efficient computing is a much needed technological advantage for future. Approximate or inexact computing is a computing paradigm that can trade energy and computing time with accuracy of output. This project proposes the approximate design and analysis of two approximate compressors with reduced area, delay and power.

The proposed compressors are utilized to implement 8x8 and 16x16 Dadda multipliers. These multipliers have high accuracy when compared with state-of-the-art approximate multipliers. The effectiveness of the proposed method is designed using Xilinx ISE 14.7

Keywords: Approximate computing, 4:2 compressors, Multiplier, Error resilient

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

Xilinx ISE 14.7
HDL: Verilog

Hardware Requirements:

Microsoft® Windows XP
Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
512 MB RAM
100 MB of available disk space

Learning Outcomes

Basics of Digital Electronics
FPGA design Flow
Introduction to Verilog Coding
Different modeling styles in Verilog

Data Flow modeling
Structural modeling
Behavioral modeling
Mixed level modeling

Concept of Approximation
Importance of Approximate computing
Drawbacks of Exact Computing in error tolerant applications
Introduction to Arithmetic Circuits
Knowledge on Compressors
Knowledge on Various Multipliers
Applications of Multipliers in real time
Scope of approximation concept in today’s world
Applications in real time
Xilinx ISE 14.7 for design and simulation
Generation of Netlist
Solution providing for real time problems
Project Development Skills:

Problem Analysis Skills
Problem Solving Skills
Logical Skills
Designing Skills
Testing Skills
Debugging Skills
Presentation Skills
Thesis Writing Skills

Demo Video

Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
DSP Core
Communications
Nano Technology
Testing

Back End Domains

Nano Technology
Cadence EDA
Low Power VLSI
Core Memories
Transistor Logic

Tools

FPGA
H-Spice
Cadence EDA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice

Others

Matlab Interfacing

H-Spice

LT-Spice