ANALYSIS OF MULTIPLIER USING 20T FULL ADDER
Objective
In this paper, A 2-bit multiplier is implemented using novel proposed full adder. The Hybrid adder designed using 20Transistors.
Abstract
In this paper, A 2-bit multiplier is implemented using novel proposed full adder. The Hybrid adder designed using 20Transistors. The configuration of this full adder uses Pass Transistor Logic and Transmission Gate Logic. This novel architecture comprises of less number of transistors compared to conventional CMOS full adder. This entire schematic is simulated using Tanner EDA.
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Block Diagram
Learning Outcomes
Learning Outcomes:
· Introduction to digital electronics.
· Basic concepts of combinational circuits.
· Advantages and Applications
· Knowledge on adders and multipliers.
· Concept of multiplier using adder.
· Tool Learning in Tanner EDA
· Analysis of design and simulation results
· Scope of universal filter in today’s world.
Paper Publishing
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