Analysis of Low Area Digital Up Down Clipping Counter for Digital In Memory Computing

Project Code :TVMABE309

Objective

To implement clipping functionality that restricts the counter output within predefined upper and lower bounds, avoiding overflow or underflow during operations.

Abstract

This project focuses on the design and analysis of a low-area digital up-down clipping counter for in-memory computing applications. The counter efficiently supports both increment and decrement operations with a clipping feature to limit the output within a specified range. The proposed design is optimized to reduce hardware area while maintaining reliable speed and low power consumption, making it suitable for memory-centric digital systems.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

· Tool Used: Tanner EDA tools for schematic and simulation

· Technology Node: 250 CMOS process.

· Counter Width: 7-bit

· Design Elements: TFF(D), RCA, FA, and DFF with clip logic.

· Optimization Goal: Reduce transistor count while ensuring accurate up/down counting with clipping at terminal values.

Learning Outcomes

· Developed a deep understanding of digital IMC architectures and energy-efficient neural processing hardware.

· Gained practical experience with transistor-level circuit design, logic optimization, and layout synthesis

· Understood the trade-offs between area, power, and performance in counter architecture.

· Acquired expertise in integrating custom counter logic into BNNs for IMC systems.

· Demonstrated proficiency with industry tools (Tanner) and simulation analysis under different process corners.

Demo Video

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Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
DSP Core
Communications
Nano Technology
Testing

Back End Domains

Nano Technology
Cadence EDA
Low Power VLSI
Core Memories
Transistor Logic

Tools

FPGA
H-Spice
Cadence EDA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice

Others

Matlab Interfacing

H-Spice

LT-Spice