Also Available Domains Tanner EDA|Cadence EDA
The main aim of this project is to implement the multiplier design with different leakage power reduction techniques. Lector, Dual VT, MTCMOS techniques are used to implement the multiplier circuit.
Power dissipation has become one of the major concerns VLSI circuit design with the rapid launching of battery operated applications. In high performance designs, the leakage component of power consumption is comparable to the switching component. This percentage will increase with technology scaling unless effective techniques are introduced to bring leakage under control. In this paper, an 8X8 multiplier is designed using different leakage power reduction techniques like MTCMOS, DUAL-Vt and LECTOR. All the above mentioned techniques are simulated using tanner tool.
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

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