Also Available Domains Transistor Logic|Tanner EDA
The main aim of this project is to implement the multiplier design with different leakage power reduction techniques. Lector, Dual VT, MTCMOS techniques are used to implement the multiplier circuit.
Power dissipation has become one of the major concerns VLSI circuit design with the rapid launching of battery operated applications. In high performance designs, the leakage component of power consumption is comparable to the switching component. This percentage will increase with technology scaling unless effective techniques are introduced to bring leakage under control. In this paper, an 8X8 multiplier is designed using different leakage power reduction techniques like MTCMOS, DUAL-Vt and LECTOR. All the above mentioned techniques are simulated using cadence EDA tool.
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Software Requirements:
Hardware Requirements:
Introduction to Multipliers
Different types of power consumption
Transistor scaling & Effects of scaling
Role of static power in lower technology nodes.
Transistors & its applications
MOS Fundamentals
NMOS/PMOS/CMOS Technologies
How to design circuits using Transistor logic?
Transistor level design for Multipliers
How to design low power, high speed area efficient transistor level circuits?
Drawbacks in CMOS technology
Scope of Low leakage circuit design in todays world.
Applications in real time
Cadence EDA tool for design and simulation
Solution providing for real time problems
Project Development Skills: