Analysis of High Speed Hybrid Full Adder
Also Available Domains Cadence EDA
Abstract
Abstract: Multiplier plays an important role in the design of FIR filters in digital signal processors (DSP). In VLSI the multipliers performance speed affects the overall speed of the system. Moreover, multiplication process uses execution time in most of the DSP devices. Hence, high speed is required in multiplier. This paper presents the analysis of a high-speed new adder using Shannon adder. The proposed hybrid adder is implemented in order to achieve higher reduction of power. The circuit simulations are done using Tanner EDA/Cadence/Hspice software. The obtained simulation results exhibit that the proposed structure performance is better in terms of Propagation delay, low power consumption and Power delay product when compared with the advanced technology in CMOS.
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Block Diagram
Specifications
Learning Outcomes
- Introduction to Digital electronics
- Introduction to Combinational circuits.
- Knowledge on Adders
- Applications of different types of adders
- Importance of Transistors
- MOS Fundamentals
- NMOS/PMOS/CMOS Technologies
- How to design circuits using Transistor logic?
- Transistor level design for Shannon adder
- How to design Proposed circuits of Hybrid adder
- Introduction to Hybrid Adders
- Importance of Hybrid logic
- Scope of Low power and fast performance adders in today’s world
- Applications in Real time.
- Tanner EDA/Cadence/H spice tool for design and simulation
- Solution providing for real time problems
- Project Development Skills:
- Problem Analysis Skills
- Problem Solving Skills
- Logical Skills
- Designing Skills
- Testing Skills
- Debugging Skills
- Presentation skills
- Thesis Writing Skills
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