Analysis and Comparison in the Energy-Delay Space of Nanometer CMOS One-Bit Full-Adders
Objective
The objective of this paper is to analyze, design and compare six significant topologies of one-bit full adders in terms of their Energy-Efficient Curves in the Energy-Delay Space
Abstract
In this paper we analyze, design and compare six significant topologies of one-bit full adders in terms of their Energy-Efficient Curves in the Energy-Delay Space. We define the simulation strategies that are adopted to make a fair comparison even among cells with very different characteristics. Each topology is designed through a methodology. The comparison of the topologies is made using a 45 nm CMOS technology in terms of simulated parameters and efficiency of the outputs generated.
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Block Diagram
Specifications
Software Requirements:
· Cadence Virtuoso
· 4nm GPDK Technology
Learning Outcomes
- Introduction to digital electronics
- Knowledge on combinational circuits
- Basics of different transistor configurations
- Tool learning in Cadence virtuoso
- Analysis of circuits and its simulation results
- Scope of full adders in today's world
Paper Publishing
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