This paper presenting an ultra-low voltage level shifter with the use of reconfigurable logic, Time borrowing Latch. As the level shifters has high demand while interconnecting sub-blocks under multiple power supply voltages. For that, an efficient design of level shifter is required. The novel design of level shifter is proposed in this paper. The purpose of employing time borrowing latch to prevent timing error. This design of level shifter is used to operate under very low voltages with 0.3V. And here regulated cross coupled pull up network is used, by that, the power utilized by the circuit is reduced and the speed is also increased. This proposed design is simulated using Tanner EDA tool employing 45nm technology files.
Keywords: Level shifter, Time borrowing Latch, RCC pull up network.
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Software Requirements:
· Tanner EDA
· Technology files: 45nm
Hardware Requirements:
· Microsoft® Windows XP
· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
· 512 MB RAM
· 100 MB of available disk space