An Ultra-Low-Voltage Level Shifter With Embedded Re-Configurable Logic and Time-Borrowing Latch Technique

This paper presenting an ultra-low voltage level shifter with the use of reconfigurable logic, Time borrowing Latch. As the level shifters has high demand while interconnecting sub-blocks under multiple power supply voltages. For that, an efficient design of level shifter is required. The novel design of level shifter is proposed in this paper. The purpose of employing time borrowing latch to prevent timing error. This design of level shifter is used to operate under very low voltages with 0.3V. And here regulated cross coupled pull up network is used, by that, the power utilized by the circuit is reduced and the speed is also increased. This proposed design is simulated using cadence virtuoso tool employing 45nm technology files.