An Ultra-Low-Voltage Level Shifter With Embedded Re-Configurable Logic and Time-Borrowing Latch Technique

Also Available Domains Transistor Logic|LT-Spice

Project Code :TVMATO1037

Abstract

This paper presenting an ultra-low voltage level shifter with the use of reconfigurable logic, Time borrowing Latch. As the level shifters has high demand while interconnecting sub-blocks under multiple power supply voltages. For that, an efficient design of level shifter is required. The novel design of level shifter is proposed in this paper. The purpose of employing time borrowing latch to prevent timing error. This design of level shifter is used to operate under very low voltages with 0.3V. And here regulated cross coupled pull up network is used, by that, the power utilized by the circuit is reduced and the speed is also increased. This proposed design is simulated using Tanner EDA tool employing 45nm technology files.

Keywords: Level shifter, Time borrowing Latch, RCC pull up network.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

· Tanner EDA

· Technology files: 45nm

Hardware Requirements:

· Microsoft® Windows XP

· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support

· 512 MB RAM

· 100 MB of available disk space

Learning Outcomes

Introduction to Digital electronics
Introduction to Level shifters
Introduction to Reconfigurable Logic
Knowledge on time borrowing concept
Importance of Transistors

MOS Fundamentals
NMOS/PMOS/CMOS Technologies
How to design circuits using Transistor logic?
Transistor level design for Level shifter
Scope of level shifters in today’s world
Applications in Real time.

Tanner EDA tool for design and simulation
Solution providing for real time problems

Project Development Skills:

Problem Analysis Skills
Problem Solving Skills
Logical Skills
Designing Skills
Testing Skills
Debugging Skills
Presentation skills
Thesis Writing Skills

Demo Video

Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
DSP Core
Communications
Nano Technology
Testing

Back End Domains

Nano Technology
Cadence EDA
Low Power VLSI
Core Memories
Transistor Logic

Tools

FPGA
H-Spice
Cadence EDA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice

Others

Matlab Interfacing

H-Spice

LT-Spice