An Ultra-Low-Power Static Contention-Free 25-Transistor True Single-Phase-Clocked Flip-Flop in 55 nm CMOS

Also Available Domains Cadence EDA|Transistor Logic

Project Code :TVMABE281

Objective

this ultra-low-power static contention-free flip-flop design addresses the need for energy-efficient flip-flop implementations in modern CMOS technologies, offering improved performance metrics

Demo Video

https://youtu.be/ZepCQet9U20?si=Zy9bk6WLfTRR9KQY
Related Topics
  • Cadence EDA
  • Finite State Machines
  • Arithmetic Core
  • DSP Core
  • Communications
  • Nano Technology
  • Testing
  • Nano Technology
  • Cadence EDA
  • Low Power VLSI
  • Core Memories
  • Transistor Logic
  • FPGA
  • H-Spice
  • Cadence EDA
  • QCA
  • Xilinx Vivado
  • Xilinx ISE
  • Tanner EDA
  • LT-Spice
  • Matlab Interfacing
  • LT-Spice

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