This paper presents the design of reversible fault tolerant architecture of logic elements of LUT (look-up table) based Field Programmable Gate Array (FPGA). The proposed logic elements are master slave Flip Flop, D-Latch and multiplexer. A new 4 ×4 and a new 6 ×6 fault tolerant reversible gates are proposed for designing efficient reversible fault tolerant D-latch, master slave Flip Flop and multiplexer, respectively. The design of the proposed logic elements achieve the improvement in terms of number of gates compared to the best known existing approach. Besides, the proposed logic elements outperform the best existing technology high in terms of quantum cost and unit delay, respectively. Finally, the efficiency of the proposed elements are clarified by implementing an n-bit adder using the proposed Configurable Logic Block (CLB) of FPGA with low power savings and better delay minimization. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx ise/vivado.