An Energy-Efficient Modified Carry Select Adder Using NCFET for Enhanced Logic Performance

Also Available Domains Transistor Logic|Low Power VLSI

Project Code :TVMABE385

Objective

Leverage NCFET Technology for Low-Power Design • Use Negative Capacitance FETs (NCFETs) to design the modified carry-select adder (CSA), taking advantage of NCFET’s steep subthreshold slope and low-voltage operation to reduce energy consumption. • Optimize the NCFET device parameters (e.g., ferroelectric layer thickness) to strike a balance between low leakage and high drive current.

Abstract

This work presents an energy-efficient modified Carry Select Adder (CSA) design using Negative Capacitance Field-Effect Transistors (NCFETs) to enhance digital logic performance. By optimizing carry propagation and reducing redundant logic paths in the conventional CSA, the proposed design achieves lower power consumption and reduced propagation delay. Leveraging the superior switching characteristics of NCFETs, the architecture improves the energy-delay product (EDP), making it highly suitable for high-speed and low-power arithmetic operations. Simulation results demonstrate significant improvements over traditional CMOS-based CSAs, making it ideal for next-generation low-power integrated circuits and digital processing applications.

Index Terms: Carry Select Adder (CSA), NCFET, Energy-efficient design, Low-power arithmetic circuits, High-speed digital logic.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Specifications

Software Requirements:

· Cadence tool

· Technology files: 45nm

Hardware Requirements:

· Microsoft® Windows XP

· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support

· 512 MB RAM

· 100 MB of available disk space

Learning Outcomes

· Understand the working principle of Carry Select Adders (CSA) and their role in digital arithmetic.

· Learn how modifying the CSA structure can reduce delay and power consumption.

· Gain knowledge of NCFET technology and its advantages over conventional CMOS in low-power, high-speed circuits.

· Understand the impact of optimized carry path selection on energy efficiency and performance.

· Apply the concepts of energy-efficient digital design for arithmetic units, DSPs, and low-power SoC applications.

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