An Energy Efficient High Performance CMOS Transmission Gate Full Adder Circuit

As single integrated circuit chip applications such as high-speed computing, data communications, large storage, micro electromechanical systems, ultra-high frequency, high-speed networking, fuel-efficient cars, crypto currencies, digital signal processing, consumer electronics, secured cryptography, robotics, space applications, smart health monitoring systems, smart buildings, and the internet of things continue to advance, there is a need for new technologies. Power-hungry algorithms including rapid Fourier algorithms, inverse discrete cosine transforms, and discrete cosine transforms are used in real-time processing of multimedia signals. They enable the chip's multiplier and subtraction logic capabilities. Since these algorithms must be implemented efficiently, adder logic is essential. This study examines the design and simulation of traditional CMOS full-adders and proposed transmission gate buffered full-adder. Using the tanner tool and a 1.5V power supply, the suggested transmission gate buffered full-adder logic circuit is implemented in a 90nm process. When the simulation results of the two logic circuits are compared, it becomes clear that the transmission gate buffered full-adder circuit, which is the primary goal in the implementation of high-speed multimedia processors.