An Efficient Design of 16 Bit MAC Unit using Vedic Mathematics

Multiply and Accumulate (MAC) is one of the primary operations used widely in signal-processing and other applications. Multiplier is the fundamental component of Digital Signal Processors (DSP's).Its parameters such as power, LUT utilization and delay decides the performance of a DSP. So, there is a need to design a power and delay efficient multiplier. In this paper, a 16-bit MAC unit is designed using an 8-bit vedic multiplier and carry-save adder. A comparison with the existing 8-bit vedic multiplier using Square-Root (SQR) Carry-Select Adder (CSLA) is presented. It is compared with a conventional array-multiplier. The entire design is implemented in Verilog HDL. Synthesis and simulations were done using Xilinx ISE Design Suite 14.5 and Vivado 2018.2. The proposed design achieves significant improvement in area and delay. In addition, a reduction in power around 9.5% is achieve