An Efficient Design for Reversible Wallace Unsigned Multiplier

In this project, we are implementing a reversible unsigned multiplier circuits in which Wallace tree method is used to reduce the depth of circuits. Here we are proposing two different multiplier designsbyrealizingthe partial products of the multiplier circuit using reversible gates. In the first method, the partial products circuit is designed using TG and FG gates so that TG is used to produce the partial products and FG for fan-out. In the second method, TG and PG gates are used to produce the partial products and no fan-out is required. In this project we have used PG gate and Feynman' block as reversible half-adder (HA) and full-adder (FA) in the adder network, respectively. In the first design, the main purpose is to decrease the depth of the circuit and increase the circuit speed. In the second design we would attempt to improve quantum parameters the number of garbage outputs, constant inputs and quantum cost. The evaluation results show that the first design, in terms of delay, is the fastest circuit. Also, the second design in terms of the number of constant inputs, garbage outputs and quantum cost is better than other designs.