An Efficient Accuracy Reconfigurable CLA Adder Designs using Complementary Logic

Also Available Domains Arithmetic Core|Xilinx Vivado

Project Code :TVPGTO389

Objective

This project presents a novel accuracy reconfigurable CLA (AR-CLA-I) adder design using 4-bit CLAs with novel approximate sum computation approach for achieving the high energy-efficiency at cost of acceptable loss in quality. Through this design, the area will be reduce

Abstract

This project presents the two efficient Accuracy Reconfigurable (AR) Carry Look Ahead Adder designs namely AR-CLA-I and AR-CLA-II. The AR-CLA-I and AR-CLA-II designs are implemented using 4-bit CLA segment with new approximate adder and complementary logic based CLA segment respectively.

The proposed AR-CLA designs can be reconfigured to achieve high energy-efficiency at cost of acceptable loss in quality. The synthesis and simulation are verified by using Xilinx ISE 14.7 version tool.

Keywords: Approximate computing, Carry Look Ahead Adder, Error tolerant Applications

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

Xilinx ISE 14.7 Tool
HDL: Verilog

Hardware Requirements:

Microsoft® Windows XP
Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
512 MB RAM
100 MB of available disk space

Learning Outcomes

Basics of Digital Electronics
FPGA design Flow
Introduction to Verilog Coding.
Different modeling styles in Verilog

Data Flow modeling
Structural modeling
Behavioral modeling
Mixed level modeling

Combinational & Sequential circuits
Knowledge on Approximate computing
Arithmetic Circuits
Carry Look Ahead Adder
About complementary Logic
Applications in real time
Xilinx ISE 14.7 for design and simulation
Generation of Netlist
Solution providing for real time problems
Project Development Skills:

Problem Analysis Skills
Problem Solving Skills
Logical Skills
Designing Skills
Testing Skills
Debugging Skills
Presentation Skills
Thesis Writing Skills

Demo Video

Front End Domains

DSP Core
Communications and Crypto Core
Design for Testability
Arithmetic Core
Nano Technology

Back End Domains

Nano Technology
Core Memories
Transistor Logic
Low Power VLSI

Tools

Cadence EDA
Xilinx Vivado
Xilinx ISE
Tanner EDA
FPGA

Others

Matlab Interfacing