An Asymmetric Dynamic Comparator for Low Offset, Low Noise, and High Speed Applications

This project presents the design and analysis of a charge-shared two-tail dynamic latch comparator intended for low-power and high-speed Successive Approximation Register Analog-to-Digital Converter (SAR-ADC) applications. With the growing demand for energy-efficient portable and biomedical electronic systems, reducing comparator power consumption without compromising speed and accuracy has become critical. In this work, Fig. 3 is newly designed based on an existing comparator architecture by incorporating a shared charge technique between the output nodes, which effectively reduces power dissipation and regeneration delay. The proposed comparator operates on a dynamic latch principle with dual tail transistors and an additional charge-sharing transistor that stabilizes the output nodes during the reset phase. The design is implemented and simulated using CMOS technology, and its performance is evaluated in terms of delay, power consumption, and power-delay product (PDP). Simulation results demonstrate that the proposed design achieves significant improvements in energy efficiency and speed compared to conventional dynamic comparators, making it highly suitable for low-power SAR-ADC architectures used in biomedical, communication, and portable electronic applications.

KEYWORDS: Successive Approximation Register-ADC, Low power, High speed, Sampling rate, Resolution, Electronic devices