An Area-Efficient High-Resolution Segmented ?-?-DAC for Built-In Self-Test Applications

This article proposes a segmented architecture for Sigma-delta (ΣΔ) digital-to-analog converters (DACs) to be utilized in built-in self-test (BIST) schemes for programmable DC voltage generators. ΣΔ-DACs are known for their high linearity; however, they come with drawbacks, such as significant digital memory requirements and the need for a large reconstruction filter with a substantial silicon area footprint. The proposed segmented DAC architecture overcomes these challenges by employing two sub-DACs, both based on ΣΔ technology. This approach offers two key advantages: a reduction in the footprint size of the reconstruction filter and substantial memory savings, leading to a simpler BIST solution. Two experimental prototypes demonstrate the benefits of the segmented ΣΔ-DAC. The first prototype is an integrated circuit (IC) design implemented using TSMC 65-nm CMOS technology. It achieves 12 bits of resolution using only 1020 memory elements, while an unsegmented ΣΔ-DAC requires 4095 elements to achieve the same resolution. This results in memory element savings. Furthermore, the segmented prototype occupies only 0.5 mm² of silicon area, whereas the unsegmented design occupies 0.77 mm² for the same resolution, presenting a silicon area reduction compared to its unsegmented counterpart. The second prototype involves implementing the segmented ΣΔ-DAC architecture using discrete components. Remarkably, this discrete prototype achieves 16 bits of resolution using just 1020 memory elements, whereas the unsegmented counterpart necessitates 65,535 bits for the same resolution. This leads to an impressive reduction in memory elements.

Keywords: Built-in self-test (BIST), low-pass filter (LPF), short-term average, sigma–delta (

) digital-to-analog converters (DACs).