An Area Efficient 1024-point Low Power Radix-22 Fft Processor with Feed-forward Multiple Delay Commutators

Radix-2k delay feed-back and radix-K delay commutator are the most well-known pipeline architecture for FFT design. This paper proposes a novel radix-22 multiple delay commutators architecture utilizing the advantages of the radix-22 algorithm, such as simple butterflies and less memory requirement. Therefore, it is more hardware efficient when implementing parallelism for higher throughput using multiple delay commutators or feed-forward data paths. Here, we propose an improved input scheduling algorithm based upon memory to eliminate energy required to shift data along the delay lines. The proposed architecture have better results in terms of delay and area. The effectiveness of the proposed method is designed using Cadence EDA