Also Available Domains FPGA|Xilinx Vivado|Xilinx ISE
The main objective of this project is to implement the approximate multiplier with reduced power and the multiplier design is implemented by employing the carry-maskable adder and the compressor
Multiplication is a key fundamental function for many error-tolerant applications. Approximate multiplication is considered to be an efficient technique for trading off energy against performance and accuracy. This proposes an accuracy-controllable multiplier whose final product is generated by a carry-maskable adder. The proposed scheme can dynamically select the length of the carry propagation to satisfy the accuracy requirements flexibly. The partial product tree of the multiplier is approximated by the proposed tree compressor. A multiplier design is implemented by employing the carry-maskable adder and the compressor. Compared with a conventional Wallace tree multiplier, the proposed multiplier reduced power consumption depending on the required accuracy. The effectiveness of the proposed method is synthesized and simulated using Xilinx ISE 14.7
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