A Very-Low-Voltage Frequency Divider in Folded MOS Current Mode Logic With Complementary n- and p-type Flip-Flops
Also Available Domains Transistor Logic|Cadence EDA
Objective
The main aim of this project is to reduce the power in Frequency divided by 16 circuit by using FCML with novel architecture.
Abstract
In this article, a static frequency divider based on Folded MOS Current Mode Logic (FMCML) is presented. The design is based on alternating FMCML flip-flops with complementary pMOS or nMOS input differential pairs since common-mode problems arise by using only one type of FMCML flip-flops. We propose a different approach: input and output common-mode levels of each divide-by-2 (DIV2) block are made compatible by alternating complementary FMCML DFF stages, thus avoiding any additional stage in between.
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.
Block Diagram
Specifications
Software Requirements:
- Tanner EDA
- Technology files: 45nm
Hardware Requirements:
- Microsoft® Windows XP
- Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
- 512 MB RAM
- 100 MB of available disk space
Learning Outcomes
- Introduction to Folded MCML Frequency dividers
- Knowledge on FMCML logic
- Knowledge on Frequency dividers
- Knowledge on Flip flops and its types
- MCML Logic & its applications.
- Current mode logic
- MCML logic
- Folded MCML Logic
- Advantages & Disadvantages
- Importance of Transistors
- MOS Fundamentals
- NMOS/PMOS/CMOS Technologies
- How to design circuits using Transistor logic?
- Transistor level design for Folded MCML Frequency dividers
- How to design low power, Folded MCML Frequency dividers using complementary p-type and n-type flip flops.
- Introduction to Analog Electronics
- Importance of Folded MCML Logic
- Scope of Current Mode Logics in today’s world
- Applications in Real time.
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