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The main aim of this project is to reduce the power in Frequency divided by 16 circuit by using FCML with novel architecture.
In this article, a static frequency divider based on Folded MOS Current Mode Logic (FMCML) is presented. The design is based on alternating FMCML flip-flops with complementary pMOS or nMOS input differential pairs since common-mode problems arise by using only one type of FMCML flip-flops. We propose a different approach: input and output common-mode levels of each divide-by-2 (DIV2) block are made compatible by alternating complementary FMCML DFF stages, thus avoiding any additional stage in between.
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