A Very Compact CMOS Analog Multiplier for Application In CNN Synapses
Also Available Domains Transistor Logic|Cadence EDA|Cadence EDA
Project Code :TVMATO544
Objective
As a application for analog cellular neural networks here in this work paper we propose CMOS analog multiplier architecture.
Abstract
This work presents a CMOS analog multiplier architecture for application as the synapse in analog cellular neural networks. The circuit comprises two voltage-mode inputs and a current-mode output. Simulated performance features obtained from a circuit design in CMOS 130 nm technology include: +100 mV input voltage range, 23 ΞΌW static power, -32 dB maximum total harmonic distortion and -3 dB bandwidth of 51.2 kHz. The active area totalizes only 40 ΞΌm2.
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Learning Outcomes
Basics of electronics and Verilog.
Related Topics
Paper Publishing
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