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The main aim of this work is to study the different adiabatic logic by using inverter designs
In the current scenario, Power utilization plays a major role in VLSI design technology. The need for low power consuming logic devices is rising rapidly and the adiabatic logic provides a great solution. This paper presents performance of adiabatic logic in CMOS with complete analysis and assessment of static adiabatic logic circuits. The current flow all the way through the circuit is controlled such that the energy dissipation because of capacitor dissipation and switching is minimized. When compared to dynamic adiabatic logic, the switching energy is reduced in static adiabatic logic. This improvement is due to the fact that facilitate the discharging operation on a node occurs just when the input signal transition requires a change in the status of the output.
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