A Sub-Threshold Differential CMOS Schmitt Trigger with Adjustable Hysteresis Based on Body Bias Technique

Also Available Domains Cadence EDA|Transistor Logic|Tanner EDA

Project Code :TVPGTO363

Objective

The main objective of this paper is to increase the noise immunity with tunable hysteresis by using sub-threshold differential CMOS Schmitt trigger. The circuit is designed in a 0.18nm standard CMOS process with a 0.6 V power supply which makes it a suitable candidate for low-power applications

Abstract

In this project, a sub-threshold differential CMOS Schmitt trigger with tunable hysteresis is proposed and it can be used to enhance the noise immunity of low-power electronic systems. By exploiting the body bias technique, Hysteresis of the proposed Schmitt trigger can be adjusted. This proposed circuit consumes less power consumption which makes it a suitable for low-power applications such as portable electronic, biomedical, and bio-implantable systems. All the designs are implemented using 180nm technology in Cadence Virtuoso.

Keywords: Differential CMOS Schmitt trigger, body bias technique, Hysteresis.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

Cadence Virtuoso
Technology files:180nm

Hardware Requirements:

Microsoft® Windows XP
Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
512 MB RAM
100 MB of available disk space

Learning Outcomes

Introduction to Schmitt trigger circuits
Transistors & its applications

Types of Transistors
Logic Gates using Transistors
Pull Up and Pull Down networks
Importance of Transistors

MOS Fundamentals
NMOS/PMOS/CMOS Technologies
How to design circuits using Transistor logic?
Transistor level design for Schmitt trigger circuits
How to design low power, high speed area efficient transistor level circuits?
Introduction to Hysteresis and static noise margins
Techniques for enhancing the hysteresis curve for improving the noise margin
Techniques for the reduction of Static power
Scope of Schmitt trigger circuits in today’s world
Applications in real time
Cadence Virtuoso tool for design
Timing analysis
Power analysis
Solution providing for real time problems
Project Development Skills:

Problem Analysis Skills
Problem Solving Skills
Logical Skills
Designing Skills
Testing Skills
Debugging Skills
Presentation Skills
Thesis Writing Skills

Demo Video

Front End Domains

DSP Core
Communications and Crypto Core
Design for Testability
Arithmetic Core
Nano Technology

Back End Domains

Nano Technology
Core Memories
Transistor Logic
Low Power VLSI

Tools

Cadence EDA
Xilinx Vivado
Xilinx ISE
Tanner EDA
FPGA

Others

Matlab Interfacing