A Static, Contention-Free, Low-Power, TSPC Dual-Edge Triggered Flip-Flop

This work presents the design and implementation of a static, contention-free, low-power True Single-Phase Clock (TSPC) dual-edge triggered flip-flop (DETFF) for high-performance and energy-efficient digital systems. Flip-flops are fundamental building blocks in synchronous circuits, and their power consumption significantly impacts overall system efficiency. Conventional single-edge triggered flip-flops require higher clock frequencies to achieve desired throughput, leading to increased dynamic power consumption.

The proposed design utilizes a dual-edge triggering mechanism, allowing data to be captured on both rising and falling edges of the clock signal, effectively reducing clock frequency requirements by half. The TSPC technique enables single-phase clock operation, simplifying clock distribution and reducing clock power. Additionally, the contention-free architecture eliminates short-circuit current paths during switching, thereby reducing power dissipation.

The flip-flop is implemented using CMOS technology and evaluated in terms of power consumption, delay, and power-delay product (PDP). Simulation results demonstrate reduced power consumption, improved efficiency, and reliable operation compared to conventional flip-flop designs, making it suitable for low-power, high-speed applications.

Keywords

TSPC Flip-Flop, Dual-Edge Triggered Flip-Flop, Low Power, Contention-Free, CMOS, Sequential Circuits, VLSI Design