A Solution for Ultra-low Bit-error-rate Interface of Superconductor-Semiconductor by using an Error-Correction-Code Encoder

Also Available Domains Communications|Xilinx Vivado

Project Code :TVMATO616

Objective

The aim of this project is to achieve low latency and high throughput to detect and correct single bit error by using Check bits.

Abstract

A solution for ultra-low bit error- rate interface of superconductor-semiconductor is designed in this project. By using an error-correction-code encoder, the low bit-error-rate requirement could be relaxed considerably. The encoder in our research encodes 32-bit original data with six extra check bits that are generated based on the theory of linear block code to correct 1-bit error. A combination of logic gate and output latch (register) controlled by clock pulses, which are physically similar to signal pulses. The implementation uses an optimized 9-stage pipelined structure achieving low latency and high throughput. This encoder is simulated in logic-gate-level and we implemented a virtual SFQ logic which performs pulse clocked logic on a realistic field-programming-gate-array to verify the design.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

Xilinx ISE Tool
HDL: Verilog

Hardware Requirements:

Microsoft® Windows XP,
Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
512 MB RAM
100 MB of available disk space

Learning Outcomes

Basics of Digital Electronics
FPGA design Flow
Introduction to Verilog Coding.
Different modeling styles in Verilog

Data Flow modeling
Structural modeling
Behavioral modeling
Mixed level modeling

Single flux quantum circuit
Knowledge Linear block codes
Arithmetic Circuits
Error correction codes
Knowledge on error rate
Applications in real time
Xilinx ISE 14.7 for design and simulation
Generation of Netlist
Solution providing for real time problems
Project Development Skills:

Problem Analysis Skills
Problem Solving Skills
Logical Skills
Designing Skills
Testing Skills
Debugging Skills
Presentation Skills
Thesis Writing Skills

Demo Video

Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
DSP Core
Communications
Nano Technology
Testing

Back End Domains

Nano Technology
Cadence EDA
Low Power VLSI
Core Memories
Transistor Logic

Tools

FPGA
H-Spice
Cadence EDA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice

Others

Matlab Interfacing

H-Spice

LT-Spice