Also Available Domains Communications and Crypto Core|Xilinx ISE
The aim of this project is to achieve low latency and high throughput to detect and correct single bit error by using Check bits.
A solution for ultra-low bit error- rate interface of superconductor-semiconductor is designed in this project. By using an error-correction-code encoder, the low bit-error-rate requirement could be relaxed considerably. The encoder in our research encodes 32-bit original data with six extra check bits that are generated based on the theory of linear block code to correct 1-bit error. A combination of logic gate and output latch (register) controlled by clock pulses, which are physically similar to signal pulses. The implementation uses an optimized 9-stage pipelined structure achieving low latency and high throughput. This encoder is simulated in logic-gate-level and we implemented a virtual SFQ logic which performs pulse clocked logic on a realistic field-programming-gate-array to verify the design.
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

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