A Slack-Based Approach to Efficiently Deploy Radix 8 Booth Multipliers

Also Available Domains Xilinx Vivado|Xilinx ISE

Project Code :TVPGFE197

Abstract

In 1951 A. Booth published his algorithm to efficiently multiply signed numbers. Since the appearance of such algorithm, it has been widely accepted that radix 4-based Booth multipliers are the most efficient. They allow the height of the multiplier to be halved, at the expense of a simple recoding that consists of just shifts and negations. Theoretically, higher radix should produce even larger reductions, especially in terms of area and power, but the recoding process is much more Complex. Notably, in the case of radix 8 it is necessary to compute 3X, X being the multiplicand. In order to avoid the penalty due to this calculation, we propose decoupling it from the product and considering 3X as an extra operation within the application’s Dataflow Graph (DFG). Experiments show that typically there is enough slack in the DFGs to do this without degrading the performance of the circuit, which permits the efficient deployment of radix 8 multipliers that do not calculate the 3X multiple. Results show that our approach is faster than radix 4 and radix 8 Booth based implementations, respectively, and more energy efficient in terms of Energy Delay Product

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Specifications

Hardware requirement

            Processor           -    Pentium –III

 

Speed                               -    1.1 GHz

RAM                                 -    1 GB (min)

Hard Disk                        -   40 GB

Floppy Drive                     -    1.44 MB

Key Board                        -    Standard Windows Keyboard

Mouse-    Two or Three Button Mouse

Monitor    -    SVGA

Software requirements

Operating System            :Windows95/98/2000/XP/Windows7

Front End                          :   Modelsim 6.3 for Debugging and Xilinx 14.3/Xilinx Vivado  for                     Synthesis and Hard Ware Implementation

This software’s where Verilog source code can be used for design implementation.

Learning Outcomes

  • Basics of Digital Electronics
  • VLSI design Flow
  • Introduction to Verilog Coding
  • Different modeling styles in Verilog

o   Data Flow modeling

o   Structural modeling

o   Behavioral modeling

o   Mixed level modeling

  • Introduction to multiplier design
  • Knowledge on partial product generation and reduction
  • About approximation computing
  • About Reversible logic
  • Applications in real time

·         Xilinx ISE 14.7/Xilinx Vivado2018.3 for design and simulation

·         Generation of Netlist.

·         Solution providing for real time problems

·         Project Development Skills:

o   Problem Analysis Skills

o   Problem Solving Skills

o   Logical Skills

o   Designing Skills

o   Testing Skills

o   Debugging Skills

o   Presentation Skills

o   Thesis Writing Skills

 

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