The main objective of this paper is to reduce the power in ANN by using the reversible logic design. The proposed architecture has been realized using a reversible multiplier followed by a reversible adder
In this project, a novel design of Artificial Neural Network (ANN) using reversible logic gates is implemented. ANN can be described as (i) Scalar weight matrix multiplication with input scalars, (ii) Sum of weighted input scalars, (iii) Scalar-to-scalar non-linearity calculation. High power consumption in ANN, is a crucial issue that can cause over reliability degradation, chip damage.
Hence the weighted sums and multiplication are performed with reversible logic for better power reduction. These modules have been implemented using Verilog HDL and the results are obtained using Xilinx ISE 14.7.
Keywords: Artificial neural network, Reversible logic, Multiplier, Low power circuits
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.
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