A Reliable Low Standby Power 10T SRAM Cell with Expanded Static Noise Margins

Also Available Domains Cadence EDA

Project Code :TVPGTO850

Objective

The main objective of this paper is to implement LP10TSRAM in order to achieve lesser power dissipation.

Abstract

This paper explores a low standby power 10T (LP10T) SRAM cell with high read stability and write-ability (RSNM/WSNM/WM). The proposed LP10T SRAM cell uses a strong cross-coupled structure consisting standard inverter with a stacked transistor and Schmitt-trigger inverter with a double-length pull-up transistor. This along with the read path separated from true internal storage nodes eliminates the read-disturbance. Furthermore, it performs its write operation in pseudo differential form through write bit line and control signal with a write-assist technique. This entire design was simulated using tanner 16nm CMOS Technology.

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Block Diagram

Specifications

Software Requirements:

· Tanner

· Technology files: 16nm

Hardware Requirements:

· Microsoft® Windows XP

· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support

· 512 MB RAM

100 MB of available disk space

Learning Outcomes

Introduction to SRAM

Different Configurations of SRAM
Working of SRAM
Knowledge on Near Threshold region
Knowledge on Sub-threshold region
Limitations & Applications.

Importance of Transistors

MOS Fundamentals
NMOS/PMOS/CMOS Technologies
How to design circuits using Transistor logic?
Transistor level design for 10T SRAM
How to design SRAM using ST inverters
Introduction to Analog Electronics
Importance of Schmitt trigger
Scope of SRAM in today’s world
Applications in Real time.

Tanner EDA tool for design and simulation
Solution providing for real time problems

Project Development Skills:

Problem Analysis Skills
Problem Solving Skills
Logical Skills
Designing Skills
Testing Skills
Debugging Skills
Presentation skills
Thesis Writing Skills

Demo Video

https://youtu.be/DRILSCjy43E?si=2HiELe_rumhRU-vz

Front End Domains

DSP Core
Communications and Crypto Core
Design for Testability
Arithmetic Core
Nano Technology

Back End Domains

Nano Technology
Core Memories
Transistor Logic
Low Power VLSI

Tools

Cadence EDA
Xilinx Vivado
Xilinx ISE
Tanner EDA
FPGA

Others

Matlab Interfacing