A Programmable and Parameterisable Reseeding Linear Feedback Shift Register
Also Available Domains Xilinx Vivado|Xilinx ISE
Objective
The main objective of this paper is to design the LFSR using Reseeding technique to generate higher number of sequences without luring the storage requirements.
Abstract
In this paper, we will design and implement a programmable and parameterizable Linear Feedback Shift Register (LFSR) for VLSI IC testing. The LFSR is used in circuit tests for test pattern generation (for exhaustive, pseudorandom, or pseudo-exhaustive testing) and as well as used for signature analysis. The complexity and size of SoCs are increasing at an alarming rate in modern times. There are errors that can occur during field manipulation of the device, attracting Logic Built in Self-Test (LBIST) over traditional ATE-based chip tests. A programmable and parameterizable LFSR can be used as test pattern generator for LBIST applications. The proposed design can generate any range of bits of vectors as per the choice of application. Also, the feedback polynomial can be parameterized to generate different length sequences. And LFSR can be configured into three different structural styles such as Fibonacci, Galois and Complete models. A Reseeding technique is introduced to leverage the LFSR to generate higher number of sequences without luring the storage requirements but testing out most of the random pattern resistant faults present in the circuit. The design is verified and analyzed in Xilinx Vivado2018.3/Xilinx ISE14.7 suite.
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Block Diagram
Specifications
Software Requirements:
· Xilinx Vivado2018.3/Xilinx ISE14.7 suite
· HDL: Verilog.
Hardware Requirements:
o Microsoft® Windows XP.
o Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support.
o 512 MB RAM.
o 100 MB of available disk space.
Learning Outcomes
· Basics of Digital Electronics.
· Concept of BIST applications.
· Different types of LFSR architectures.
· Concept of Reseeding LFSR.
· Different applications of LSSR.
· Introduction to Verilog Coding.
· Different modeling styles in Verilog.
· Data Flow modeling.
· Structural modeling.
· Behavioral modeling.
· Mixed level modeling.
· Introduction to LFSR design.
· About reseeding LFSR architecture process.
· Knowledge on generation of pseudo random test pattern generations.
· About approximation computing.
· Applications in real time.
· XilinxVivado2018.3/Xilinx ISE14.7 Suite for design and simulation.
· Generation of Netlist.
· Solution providing for real time problems.
· Project Development Skills:
o Problem Analysis Skills.
o Problem Solving Skills.
o Logical Skills.
o Designing Skills.
o Testing Skills.
o Debugging Skills.
o Presentation Skills.
o Thesis Writing Skills.
Paper Publishing
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