A Novel Ultra-Compact FPGA-Compatible TRNG Architecture Exploiting Latched Ring Oscillators
Also Available Domains Xilinx Vivado|Xilinx ISE
Objective
The main aim of this paper is to generate the true random numbers with less FPGA resources. It will be applicable when we introduce the LRO. The randomness and metastability reduction are the added advantages.
Abstract
In this brief we present a novel, ultra-compact, True Random Number Generator (TRNG) architecture. The proposed Latched Ring Oscillator (LRO) TRNG allows the generation of a TRNG bit from a single FPGA Slice. Despite its very compact structure, the proposed LRO-TRNG relies on both meta-stability and accumulated jitter as entropy sources, and exhibits very good results in terms of unpredictability and randomness. The proposed architecture has been designed and simulated on Xilinx vivado/Xilinx ISE tool.
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Block Diagram
Specifications
Specifications:
Software Requirements:
· Xilinx vivado2018.3/Xilinx ISE Tool
· HDL: Verilog
Hardware Requirements:
· Microsoft® Windows XP
· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
· 512 MB RAM
· 100 MB of available disk space
Learning Outcomes
Learning Outcomes:
- Basics of Digital Electronics
- VLSI design Flow
- Introduction to Verilog Coding
- Different modeling styles in Verilog
o Data Flow modeling
o Structural modeling
o Behavioral modeling
o Mixed level modeling
- Introduction to sequential circuits
- Knowledge on Latched Ring Oscillator (LRO).
- Knowledge on d-latch.
- Knowledge on random pattern generation process.
- Applications in real time
· Xilinx ISE 14.7/Xilinx Vivado2018.3 for design and simulation
· Generation of Netlist
· Solution providing for real time problems
· Project Development Skills:
o Problem Analysis Skills
o Problem Solving Skills
o Logical Skills
o Designing Skills
o Testing Skills
o Debugging Skills
o Presentation Skills
o Thesis Writing Skills
Related Projects
Paper Publishing
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