A Novel Technique to Improve Performance Evaluation of Domino Logic Circuits in CMOS and FinFET Technology
Also Available Domains Cadence EDA|Cadence EDA
Objective
In this paper, a high-speed and Ultra-Low power FinFET technology-based domino OR circuit is discussed with various OR domino logic are simulated in the MOS and FinFET (SG & LP modes) technologies
Abstract
In this project, a Low Power Stacked (LPS) FinFET based Domino logic for the 8 input OR gate is proposed. As the silicon industries miniaturizing the device size and increasing the performance day by day to implement more functionality in digital ICs, we elaborate different techniques which is used to design domino logic circuits. Power consumption can be minimized without deteriorating the performance of the circuit and the efficiency of the circuit can be increases with proposed technique. With low power characteristics and great performance improvement in FinFET devices changes are obtained in higher ION/IOFF ratio and the leakage current is reduced and it fastens the switching speed.
Keywords: CMOS, FinFET, Low Power, Domino.
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.
Block Diagram
Specifications
Software Requirements:
- Cadence Virtuoso
- Technology files:180nm
Hardware Requirements:
- Microsoft® Windows XP
- Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
- 512 MB RAM
- 100 MB of available disk space
Learning Outcomes
- Introduction to FinFET and domino logic circuits
- Transistors & its applications
- Types of Transistors
- Logic Gates using Transistors
- Pull Up and Pull Down networks
- Importance of Transistors
- MOS Fundamentals
- NMOS/PMOS/CMOS Technologies
- How to design circuits using Transistor logic?
- Transistor level design for both FinFET and domino logic circuits
- How to design low power, high speed area efficient transistor level circuits?
- Drawbacks in CMOS technology
- Importance of Static power consumption in lower technology nodes
- Techniques for the reduction of Static power
- Scope of FinFET and domino logic in today’s world
- Applications in real time
- Cadence Virtuoso for design and simulation
- Solution providing for real time problems
- Project Development Skills:
- Problem Analysis Skills
- Problem Solving Skills
- Logical Skills
- Designing Skills
- Testing Skills
- Debugging Skills
- Presentation Skills
- Thesis Writing Skills
Paper Publishing
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