A Novel Technique to Improve Performance Evaluation of Domino Logic Circuits in CMOS and FinFET Technology

Also Available Domains Low Power VLSI|Cadence EDA

Project Code :TVMATO440

Objective

In this paper, a high-speed and Ultra-Low power FinFET technology-based domino OR circuit is discussed with various OR domino logic are simulated in the MOS and FinFET (SG & LP modes) technologies

Abstract

In this project, a Low Power Stacked (LPS) FinFET based Domino logic for the 8 input OR gate is proposed. As the silicon industries miniaturizing the device size and increasing the performance day by day to implement more functionality in digital ICs, we elaborate a different technique which is used to design domino logic circuits. Power consumption can be minimized without deteriorating the performance of the circuit and the efficiency of the circuit can be increases with proposed technique.

With low power characteristics and great performance improvement in FinFET devices changes are obtained in higher ION/IOFF ratio and the leakage current is reduced and it fastens the switching speed. All the designs are implemented using 180nm technology in Cadence Virtuoso.

Keywords: CMOS, FinFET, Low Power, Domino.

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