A Novel Low Power, Low Area Array Multiplier Design for DSP Applications

This paper presents a novel low power and low area array multiplier utilizing a carry save adder. Unlike conventional parallel array multipliers, the proposed design eliminates the final addition stage. Both conventional and proposed multipliers are synthesized using 16-T full adders. Among various adder types evaluated—Transmission Gate, Transmission Function, and 14-T and 16-T full adders—the 16-T full adder demonstrates superior energy efficiency.

In the proposed 4x4 multiplier architecture, carry bits are added without employing a Ripple Carry Adder (RCA) in the final stage. Instead, carries are fed into the input of the next left column, effectively optimizing transistor count. This results in a reduction of 56 transistors, albeit with a trade-off between power and area.

For a 90nm technology at a supply voltage of 1.2V, the proposed multiplier exhibits compelling performance metrics compared to the conventional approach. Specifically, it achieves a reduction in power consumption, increase in speed, and a significant decrease in energy consumption. These findings underscore the efficiency gains and benefits of the proposed design for DSP applications demanding low power and area-efficient solutions.