A Novel Energy Efficient 4-Bit Vedic Multiplier Using Modified GDI Approach at 32 nm Technology

This paper proposes a novel energy-efficient 4-bit Vedic multiplier designed using a modified Gate Diffusion Input (GDI) technique implemented at 32 nm CMOS technology. Vedic mathematics, derived from ancient Indian scriptures, provides highly efficient algorithms for arithmetic operations. The Urdhva Tiryagbhyam sutra of Vedic mathematics is employed here as the core multiplication algorithm due to its inherent parallelism, which reduces the number of computational steps and minimizes partial product generation delay. The Gate Diffusion Input (GDI) technique is a low-power design methodology that realizes complex logic functions using only two transistors per cell, drastically reducing transistor count, power consumption, and silicon area compared to conventional CMOS implementations. In the proposed design, a modified GDI approach is adopted to overcome the threshold voltage drop limitations of standard GDI cells, ensuring full-swing output and improved noise margin. The 4-bit Vedic multiplier is constructed using GDI-based half adders, full adders, and AND gates. The complete design is simulated using Tanner EDA tool with 32 nm technology files. Results confirm that the proposed multiplier achieves significant reduction in power consumption, propagation delay, and Power Delay Product (PDP) compared to existing CMOS and standard GDI-based multiplier designs, making it an ideal candidate for low-power embedded and portable digital systems.

 

Index Terms—Vedic multiplier, GDI technique, modified GDI, low power VLSI, Urdhva Tiryagbhyam, 32 nm CMOS, energy efficient design, power delay product, approximate computing, digital arithmetic