A Novel Design of Power-Efficient and Accurate Approximate Multiplier using Approximate Compressors and Approximate Adders

Approximate multipliers represent a burgeoning paradigm shift in approximate computing. They achieve significant reductions in power consumption, area, and delay at the expense of some computational fidelity. Approximate computing is widely used for better performance in image processing, neural networks, and wireless communication. This paper proposes a novel approximate multiplier architecture that uses approximate compressors and approximate adders (half and full) to achieve appreciable power savings. An error compensation mechanism ensures acceptable accuracy bounds, this approach simplifies complex arithmetic operations while maintaining computational efficiency. The proposed designs are implemented using Verilog HDL, and their functionality is verified through simulation and synthesis using the Xilinx Vivado tool. In the baseline design, the proposed designs, design 1 and design 2, reduced power consumption by 59.16% and 65.93% and have an average accuracy of 93. 14% and 91. 98%, respectively