A Novel BIST Method for Multi-Port Register Files

Project Code :TVMAFE686

Objective

The objective of this project is to design and implement a novel Built-In Self-Test (BIST) method for multi-port register files to enhance testing efficiency and fault detection capability. It focuses on developing a self-testing architecture that reduces external testing complexity and improves reliability. The proposed BIST scheme will be analyzed for parameters such as fault coverage, area overhead, and testing time. Simulation and verification will be performed to validate the functionality and effectiveness of the design. The overall goal is to achieve a high-performance, low-cost, and reliable testing solution for modern VLSI register file architectures

Abstract

Abstract:

A novel test method is proposed to test 3nm technology register files with large numbers of read and write ports. Due to the large number of bit lines and word lines present in a single cell, it is difficult to correctly test relevant combinations and trigger faulty behavior.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

· Xilinx ISE Tool/Xilinx Vivado

· HDL: Verilog

Learning Outcomes

· Understand testing challenges in nanoscale multi-port memories

· Analyze coupling faults in bit lines and word lines

· Learn BIST-based memory test methodologies

· Design test strategies with minimal area overhead

· Evaluate trade-offs between test time and fault coverage

Apply automated test generation tools in VLSI testing

Demo Video

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Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
DSP Core
Communications
Nano Technology
Testing

Back End Domains

Nano Technology
Cadence EDA
Low Power VLSI
Core Memories
Transistor Logic

Tools

FPGA
H-Spice
Cadence EDA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice

Others

Matlab Interfacing

H-Spice

LT-Spice