A Novel Architecture for Multiplier and Accumulator Unit Using Parallel Prefix Adders

The objective of “A Novel Architecture for Multiplier and Accumulator Unit Using Parallel Prefix Adders” is to design an efficient multiply–accumulate (MAC) unit for digital signal processing by integrating parallel prefix adders such as Kogge?Stone, Brent?Kung, Han?Carlson, and Ladner?Fischer into the multiplier and accumulator architecture to improve overall speed, power efficiency, and area performance compared to conventional designs, with the unit described and evaluated using Verilog HDL and synthesized on FPGA technology.