Also Available Domains Arithmetic Core|Xilinx Vivado
The main objective of this project is to implement the high performance MAC unit by using dadda multiplier and high speed adders like Parallel prefix adders.
The most widely used operation in digital signal processing is Multiply and Accumulate (MAC) unit, it performs both multiplication and addition. The area occupied by the MAC unit and the power consumed will largely affect the performance and speed of the electronic system. In this paper we are implementing MAC unit by using parallel prefix adder, this adder is the high-speed adder to improve the speed of MAC unit and multiplication purpose. In this design Dadda multiplier with Han-Carlson adder is proposed. This MAC unit is designed by using Verilog HDL, as well as synthesized and simulated using Xilinx ISE 14.7.
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Software Requirements:
Hardware Requirements: