A Novel Architecture for Multiplier and Accumulator Unit by using Parallel Prefix Adders

Also Available Domains Xilinx Vivado|Xilinx ISE

Project Code :TVMAFE364

Objective

The main objective of this project is to implement the high performance MAC unit by using dadda multiplier and high speed adders like Parallel prefix adders.

Abstract

The most widely used operation in digital signal processing is Multiply and Accumulate (MAC) unit, it performs both multiplication and addition. The area occupied by the MAC unit and the power consumed will largely affect the performance and speed of the electronic system. In this paper we are implementing MAC unit by using parallel prefix adder, this adder is the high-speed adder to improve the speed of MAC unit and multiplication purpose. In this design Dadda multiplier with Han-Carlson adder is proposed. This MAC unit is designed by using Verilog HDL, as well as synthesized and simulated using Xilinx ISE 14.7.

Keywords: MAC, Dadda multiplier, parallel prefix adders.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

Xilinx ISE 14.7 version Tool
HDL: Verilog

Hardware Requirements:

Microsoft® Windows XP
Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
512 MB RAM
100 MB of available disk space

Learning Outcomes

Basics of Digital Electronics
VLSI design Flow
Introduction to Verilog Coding
Different modeling styles in Verilog

Data Flow modeling
Structural modeling
Behavioral modeling
Mixed level modeling

Introduction to DSP
Knowledge on MAC unit
Different parallel prefix adders
Knowledge on array multiplier and Dadda multiplier
Study on various adders
Applications in real time
Xilinx ISE 14.7 for design and simulation
Generation of Netlist
Solution providing for real time problems
Project Development Skills:

Problem Analysis Skills
Problem Solving Skills
Logical Skills
Designing Skills
Testing Skills
Debugging Skills
Presentation Skills
Thesis Writing Skills

Demo Video

Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
DSP Core
Communications
Nano Technology
Testing

Back End Domains

Nano Technology
Cadence EDA
Low Power VLSI
Core Memories
Transistor Logic

Tools

FPGA
H-Spice
Cadence EDA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice

Others

Matlab Interfacing

H-Spice

LT-Spice