A Novel 18T Hybrid Master-Slave Flip-Flop With Low Power and Delay

This paper presents a novel 18-transistor hybrid master-slave flip-flop called the Proposed Flip-Flop Circuit (PFC), designed using 45nm CMOS technology with a single-phase clock. The circuit is divided into two sections — the master section, which uses a level restoring circuit to retain data, and the slave section, which employs a transistor stacking technique to minimize leakage current. The PFC is primarily optimized for three key performance metrics: power consumption, propagation delay, and chip area. In terms of average power consumption, PFC outperforms existing designs such as ADTFF, HFF, 18TSPC, LSRFF, TCFF, and CSFF by margins ranging from 26.02% to 50.68%. It also achieves significant speed improvements by reducing the clock-to-Q delay by 23.32% to 38.79% compared to those same designs. Monte Carlo simulations conducted over 1000 samples validated the PFC's average power consumption and C-to-Q delay performance, confirming its robustness across manufacturing variations. By reducing the PMOS transistor count and using only 4 clock signals (compared to 5 or more in existing designs), the PFC achieves a smaller layout area and lower clock power overhead, making it well-suited for high-speed, energy-efficient applications such as smartphones, laptops, and portable electronics operating at up to 1 GHz.

KEYWORDS:   Master-slave flip-flop, low power, Monte Carlo simulations, clock overloading, CMOS, switching activity, leakage power