A New Input Grouping and Sharing Method to Design Low Complexity FFT Implementation
Also Available Domains FPGA|DSP Core|Arithmetic Core|Testing
Objective
This research paper likely presents a detailed analysis of the proposed input grouping and sharing methods, including comparisons with existing approaches, performance benchmarks, and potential applications such as digital signal processing, image processing, or wireless communication systems where FFT algorithms are commonly used.
Abstract
- The Fast Fourier Transform (FFT) is a widely applied algorithm in digital signal processing and communication systems. This brief introduces a novel low-power and low-complexity FFT architecture. An input grouping method is adopted to minimize the number of multiplications involving inputs and FFT twiddle factor coefficients. Additionally, a partial sum sharing scheme is proposed to efficiently reuse hardware resources, significantly reducing adder costs. Logic synthesis results on ASIC demonstrate that the proposed 16-point FFT architecture.
Keywords— FFT, twiddle factors, partial sum sharing.
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.
Block Diagram
Specifications
Software Requirements:
VIVADO 2018.3
Hardware Requirements:
· Microsoft® Windows XP
· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
· 512 MB RAM
· 100 MB of available disk space
Learning Outcomes
- Basics of Digital Electronics
- VLSI design Flow
- Applications in real time
· VIVADO for design and simulation
· Solution providing for real time problems
· Project Development Skills:
o Problem Analysis Skills
o Problem Solving Skills
o Logical Skills
o Designing Skills
o Testing Skills
o Debugging Skills
o Presentation Skills
o Thesis Writing Skills
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