A New Design of XOR-XNOR gates for low power application

The paper discusses the significance of XOR and XNOR gates within digital systems, particularly in arithmetic and encryption circuits. It introduces a novel approach that combines these gates utilizing only six transistors, aimed at enhancing energy efficiency for low-power applications. To evaluate the effectiveness of this new design, it was compared against other existing XOR-XNOR configurations through simulations conducted in the Cadence environment, employing 45nm CMOS technology. These simulations covered various aspects such as delay, power usage, and the area, across a range of supply voltages extending from 0.5v The findings indicate that the proposed design not only exhibits reduced power consumption but also maintains a complete voltage swing.

Keywords-XOR-XNOR gate, pass transistor logic(PTL) ,low power, delay