Also Available Domains Low Power VLSI
The main objective of this project is to design an effective performance PLL using novel structure of PFD using Dynamic inverter and frequency divider structures in the the design of final PLL circuit.
This paper introduces a modified design of CMOS dynamic Phase Frequency Detector (PFD). The proposed PFD circuit (PPFD) is designed, simulated and the results obtained are analyzed. In order to reduce dead zone, internal signal routing is used in the PPFD circuit. To extend, Phase Locked Loop (PLL) is designed and it is verified with Frequency Divider (FD) circuit. There is a decrease in area of the PLL circuit with 55 transistors and dissipates power of 89.2 pW for 1.8 V power supply. The pre-layout simulation result shows that the PPFD circuit has an elimination of a dead zone. Further, it works with the high speed and reduced power operated in the reference frequency.
Key words:-PFD, Dead Zone, VCO, Power, PLL
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Software Requirements:
Hardware Requirements:
· Introduction to Analog & Digital Electronics
· Necessity of PLL.
· Advantages & Applications of PLL.
· Basics of VCO
o Different configurations of VCO
· Knowledge on Low pass filter
· Design of PLL in Cadence
· Analysis of simulation results & Outputs
· Scope of PLL in today’s world.
· Real time applications of PLL.