A Mixed Style Multiplier Architecture for Low Dynamic and Leakage Power Dissipation

Project Code :TVMAFE545

Objective

The main aim of doing this work is to neglect the logic blocks when their function is not required which tend to decrease latency and area which are due to transmission gates.

Abstract

Abstract: In order to reduce power dissipation or power consumption we have proposed an efficient design of combinational circuits by making a mixed style multiplier architecture. The main aim of doing this work is to neglect the logic blocks when their function is not required which tend to decrease latency and area which are due to transmission gates. This technique is called bypassing i.e., by not considering the multiplication operation when multiplier is ‘0’. By applying this technique we observe a decrease in dynamic power especially in the array multiplier circuit because of their regular arrangements, it is lacking area reduction and fast speed of the tree multipliers. Hence a combination of traditional tree based design and neglecting the unnecessary logic blocks will produce an efficient circuit which is having improvement in performance parameters.

Keywords: Combinational circuits, multiplier, transmission gates, bypassing, dynamic power, array multiplier.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

· Xilinx Vivado 2018.3 / Xilinx ISE 14.7

Minimum Hardware Requirements:

· Microsoft® Windows XP

· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support

· 512 MB RAM

· 100 MB of available disk space

Learning Outcomes

Learning Outcomes:

Introduction to Digital Electronics
Analysis of digital circuits
Importance of Multipliers
Disadvantages of existing multipliers
Knowledge on bypass technique

Xilinx ISE/Vivado software tool for code and simulation
Solution providing for real time problems
Project Development Skills:

Problem Analysis Skills
Problem Solving Skills
Logical Skills
Designing Skills
Testing Skills
Debugging Skills
Presentation skills
Thesis Writing Skills

Demo Video

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Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
DSP Core
Communications
Nano Technology
Testing

Back End Domains

Nano Technology
Cadence EDA
Low Power VLSI
Core Memories
Transistor Logic

Tools

FPGA
H-Spice
Cadence EDA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice

Others

Matlab Interfacing

H-Spice

LT-Spice